At the present, in Japan, provision of a digital broadcasting service using a successor to the BS4 scheduled to be launched as a broadcasting satellite is being discussed at the Radio Regulatory Council. In this digital broadcasting service, 8 SPK (Phase Shift Keying), QPSK (Quadrature PSK), and BPSK (Binary PSK) are defined as channel coding systems.
FIG. 1 is a block diagram of an example of the configuration of a transmitter and a receiver. The transmitter 1 is comprised of a video, audio, or other information source 2, a coder 3, a puncturing unit 4, and a mapping unit 5. The information source 2 outputs data to be coded and transmitted to the coder 3. The coder 3 performs trellis coding on input 1-bit data by the coding rate R=1/2 and outputs it to the puncturing unit 4 as a 2-bit coded word. The puncturing unit 4 punctures the input 2-bit data and outputs it to the mapping unit 5. The mapping unit 5 assigns the input 2-bit coded word to one signal point among four signal points shown in FIG. 5 by an quadrature modulation system and outputs an I-signal and Q-signal of the signal point to a channel 6.
A receiver 7 is comprised of a bit insertion unit 8, a decoder 9, and decoded information 10. The bit insertion unit 8 inserts bits into the received signals (I, Q) input via the channel 6 and outputs them to the decoder 9. The decoder 9 performs trellis decoding on the input signal and outputs it as decoded information 10. The decoded information 10 shows decoded data. An image and sound can be obtained by reproducing the decoded information 10 with a not shown reproducing apparatus.
Information of the state metric output from the decoder 9 is supplied to a monitoring circuit 11. The monitoring circuit 11 determines an error rate on the channel 6 and outputs the information as error rate information 12. The error rate information 12, for instance, is used as data when adjusting the orientation of the antenna for receiving the data in a direction giving the lowest error rate.
FIG. 2 is a block diagram showing the configuration of a coder 3. The coder 3 is a convolutional coder. An input 1-bit data b0 is coded to 2-bit data (c1, c0) and output. The output 2-bit data c1, c0 is generated by calculating the data b0 by a processor comprising delay circuits 21 and 22 and exclusive OR circuits 23 and 24.
That is, the data b0 is input to the delay circuit 21, the exclusive OR circuit 23, and the exclusive OR circuit 24. The data b0 input to the delay circuit 21 is delayed by one unit time and output to the delay circuit 22 and the exclusive OR circuit 23. The data input to the delay circuit 22 is further delayed for one unit time and output to the exclusive OR circuits 23 and 24. The exclusive OR circuit 23 calculates the exclusive OR of the three bits of data, that is, the data b0 currently input in the coder 3, the data input to the coder 3 one time unit before, and further the data input to the coder 3 two time units before, to generate the output data c1.
The exclusive OR circuit 24 calculates the exclusive OR of the data b0 currently input in the coder 3 and the data input to the coder 3 two time unit before to generate an output data c0.
The output data (c1, c0) output from the coder 3 are input to the puncturing unit 4 in this way. The puncturing unit 4 outputs the input data to the mapping unit 5 as is when outputting the data of the coding rate R=1/2 to the channel 6 and punctures the input data and outputs it to the mapping unit 5 when outputting data of the coding rate R=3/4 to the channel 6.
FIGS. 3A and 3B are views for explaining the puncturing. As shown in FIG. 3A, the puncturing unit 4 punctures the input data (c1, c0) in accordance with the puncturing table shown in FIG. 3B and outputs the data (p1, p0).
In the puncturing table shown in FIG. 3B, “1” shows the input data output as the data p0 or data p1 and “0” shows the input data not output (erased). For instance, the data shown in FIG. 4B is output when the data shown in FIG. 4A is input.
That is, as shown in FIG. 4A, when data X1 to X6 are input as the input data c1 and the data Y1 to Y6 are input as the input data c0 to the puncturing unit 4, since these are input in the order of the data c0, c1, when the data are sequentially input in the order of Y1, X1, Y2, X2, . . . , Y6, X6 to the puncturing unit 4, as shown in FIG. 4B, the data X1, Y3, X4, and Y6 are output as the output data p1 and the data Y1, X2, Y4, and X5 are output as the output data p0. Note that since the output data is output in the order of the data p0, p1, the data is output from the puncturing unit 4 in the order of Y1, X1, X2, Y3, Y4, X4, X5, and Y6.
The input data Y1, X1 are output as output data p0, p1 as is since they correspond to positions of the value 1 of the puncturing table, but the input data Y2 is deleted since it corresponds to a position of a value 0 of the puncturing table. The next output data X2 (corresponding to a position of a value 1 of the puncturing table) is output as the data p0. Below, in the same way, data corresponding to a position of a value 0 of the puncturing table are deleted and data corresponding to a position of a value 1 of the puncturing table are output.
The data output from the puncturing unit 4 in this way are mapped onto the signal points in the quadrature coordinate system based on the I-axis and Q-axis as shown in FIG. 5 by the mapping unit 5. The signal points are arranged at equal intervals 90 degrees apart. “p1” shown in FIGS. 3A and 3B is the MSB (most significant bit) in the signal point assignment, while “p0” is the LSB (least significant bit) in the signal point assignment. That is, a signal point assignment may be expressed as (p1, p0).
The data mapped by the mapping unit 5 is input to the bit insertion unit 8 of the receiver 7 through the channel 6. FIGS. 6A and 6B are views explaining bit insertion. Bit insertion is processing opposite to the puncturing performed in the puncturing unit 4, that is, processing for outputting received data as is to the decoder 9 when receiving data of the coding rate R=1/2 and inserting deleted data (bits) when receiving data of the coding rate R=3/4.
As shown in FIG. 6A, the bit insertion unit 8 inserts bits in the data (p′1, p′0) from the transmitter 1 through the channel 6 in accordance with the depuncturing table shown in FIG. 6B and outputs the output data (c′1, c′0). A value 1 of the depuncturing table shown in FIG. 6B indicates to output the input data as is, while the value 0 indicates to insert 0 (insert a bit).
When for example input data shown in FIG. 7A (data output from the puncturing unit 4 and shown in FIG. 4B) is input to the bit insertion unit 8, the data shown in FIG. 7B is output. The data transmitted from the transmitter 1 is in the order of the data p0, p1, so the order of input into the bit insertion unit 8 of the receiver 7 also becomes the data p′0, p′1. Further, the order of the data output from the bit inserted unit 8 becomes the data c′0, c′1.
Note that the data p′0, p′1 show the data p0, p1 output from the transmitter having the possibility of generation of error due to the effect of noise or distortion in the channel 6.
Therefore, the data X2 input as the input data p′0 is data corresponding to a position of a value 0 of the depuncturing table, so is output as the data c′0 in a form with 0 inserted instead of the input data X2. The data X2 is output as the data c′1. In this way, input data positioned at a value 0 is output with 0 inserted.
Data with a bit inserted by the bit insertion unit 8 in this way is output to the decoder 9.
FIG. 8 is a block diagram of the inner configuration of the decoder 9. The decoder 9 is comprised of a branch metric generator 31 (hereinafter referred to as a “BM generator 31”), an add, compare, and select (ACS) circuit 32, and a path memory 33. The signal input to the decoder 9 is first input to the BM generator 31 calculating the square of the Euclidean distance from a received signal point with the noise and distortion of the channel to a signal point to originally be received and generating the same as a branch metric. The branch metrics generated at the BM generator 31 are cumulatively added and compared in accordance with a convolutional coding trellis by the ACS circuit 32 to calculate the state metric of each state.
FIG. 9 is a trellis transition diagram for explaining the calculation of a state metric performed by the ACS circuit 32. As the paths in the state 00 at the time t+1, two paths may be considered: the path of the case where the branch metric BM00 is selected at the state 00 at the time t and the path of the case where the branch metric BM11 is selected at a state 01 at the time t. The value obtained by adding the value of the branch metric BM00 to the state metric of the state 00 at the time t and the value obtained by adding the value of the branch metric BM11 to the state metric of the state 01 at the time t are compared and the path with the smaller value is used as the state metric of the state 00 at the time t+1.
Similarly, the state metrics of the states 01, 10, and 11 at the time t+1 are calculated.
The ACS circuit 32, as described above, controls the path memory 33 while inferring the state transition at the coding side (transmission side). If there is no noise or distortion on the channel, the input signal matches with the original transmission signal point, so the BM generator 31 generates 0 for the branch metric relating to the transmission signal point and the square of the distance between the signal points for other branch metrics. Therefore, when these branch metrics are cumulatively added in accordance with the state transition diagram and the state metric calculated in the ACS circuit 32, the state metric remains 0 for the original path, but the state metric is a large value for other paths, so the transmission signal sequence can be inferred from this.
Here, consider the case where the input signal includes noise. Since the input signal is comprised of the original transmission signal point plus noise, the branch metric relating to the original transmission signal point does not always become 0 and has indefiniteness depending on the noise power. In the same way, for other branch metrics as well, the square of the distance between signal points also has indefiniteness depending on the noise power.
However, when the noise power is small, the ACS circuit 32 cumulatively adds the branch metrics in accordance with the state transition diagram and calculates the state metric. Since the state metric is a small value for the original path, but the state metric has a large value for other passes, it is possible to estimate the transmission signal sequence.
FIG. 10 is a block diagram of the configuration of the ACS circuit 32. The ACS circuit 32 is comprised of the state 00 generating unit 41, state 01 generating unit 42, state 10 generating unit 43, and state 11 generating unit 44 for finding the state metrics for the states 00, 01, 10, and 11. The state 00 generating unit 41 is comprised of adders 45-1 and 46-1 and a selector 47-1. The state metric of the state 00 and branch metric BM00 at the time t are input to the adder 45-1 and added. In the same way, the state metric of the state 01 and branch metric BM11 at the time t are input to the adder 46-1 and added.
The selector 47-1 compares the values input from the adder 45-1 and the adder 46-1 and outputs the smaller value to a register 48-1. The register 48-1 stores the value of the state metric of the state 00 at the time t+1, output from the selector 47-1, as a value at the time when finding the state metric of the state 00 at the next time t+2, and outputs it to the path memory 33.
The state 01 generating unit 42 is comprised of the adders 45-2 and 46-2 and the selector 47-2. The state metric of the state 10 and branch metric BM10 at the time t are input to the adder 45-2 and added. The state metric of the state 11 and the branch metric BM01 at the time t are input to the adder 46-2 and added. The selector 47-2 compares the values input from the adder 45-2 and the adder 46-2 and outputs the smaller value to a register 48-2. The register 48-2 stores the value of the state metric of the state 01 at the time t+1, output from the selector 47-2, as a value at the time when finding the state metric of the state 01 at the next time t+2, and outputs it to the path memory 33.
The state 10 generating unit 43 is comprised of the adders 45-3 and 46-3 and the selector 47-3. The state metric of the state 00 and the branch metric BM11 at the time t are input to the adder 45-3 and added. The state metric of the state 01 and the branch metric BM00 at the time t are input to the adder 46-3 and added. The selector 47-3 compares the values input from the adder 45-1 and the adder 46-3 and outputs the smaller value to a register 48-3. The register 48-3 stores the value of the state metric of the state 10 at the time t+1, output from the selector 47-3, as a value at the time when finding the state metric of the state 10 at the next time t+2, and outputs it to the path memory 33.
The state 11 generating unit 44 is comprised of the adders 45-3 and 46-3 and the selector 47-4. The state metric of the state 10 and the branch metric BM01 at the time t are input to the adder 45-4 and added, while the state metric of the state 11 and branch metric BM10 at the time t are input to the adder 46-4 and added. The selector 47-4 compares the values input from the adder 45-1 and the adder 46-4 and outputs the smaller value to a register 48-4. The register 48-4 stores a value of the state metric of the state 11 at the time t+1, output from the selector 47-4, as the value at the time when finding the state metric of the state 11 at the next time t+2, and outputs it to the path memory 33.
However, the bit length in the above ACS circuit 32 is limited, so overflow occurs due to the addition of the branch metrics, therefore processing is necessary to prevent overflow from occurring. The processing to prevent overflow from occurring in this way is called “normalization”. FIG. 11 shows the configuration of the ACS circuit 32 for calculating a state metric while performing normalization.
In the configuration of the ACS circuit 32 shown in FIG. 11, the value output from the state 00 generating unit 41 is supplied to the register 48-1 through the subtracter 51-1, the value output from the state 01 generating unit 42 is supplied to the register 48-2 through the subtracter 51-2, the value output from the state 10 generating unit 43 is supplied to the register 48-3 through the subtracter 51-3, and the value output from the state 11 generating unit 44 is supplied to the register 48-4 through the subtracter 51-4. The values output from the registers 48-1 to 48-4 are input to the path memory 33 and the minimum value processor 52.
The minimum value processor 52 calculates the minimum value of the state metrics output from the registers 48-1 to 48-4 and outputs the value to the subtracters 51-1 to 51-4, the path memory 33, and the monitoring circuit 11. The subtracters 51-1 to 51-4 subtract the value input from the minimum value processor 52 from the values input from the state generating units 41 to 44 respectively corresponding to the subtracters 51-1 to 51-4. In this way, normalization is carried out.
FIG. 12 is a block diagram of the configuration of the monitoring circuit 11. The monitoring circuit 11 is comprised of an accumulator 61 and a table 62. The accumulator 61 cumulatively adds the values of the minimum state metric for a predetermined time and outputs the cumulative total to the table 62. The table 62 is comprised of a ROM (read only memory) and the like and determines the noise of the channel by using a table establishing correspondence between a value output from the accumulator 61 and noise.
FIG. 13 is a block diagram of the configuration of the accumulator 61. A timer 71 generates a pulse at a predetermined cycle and supplies the pulse to a minimum SM (status metric) value accumulator 72. The minimum SM value accumulator 72 receives as input the minimum value of the state metric output from the minimum value processor 52 (FIG. 11) and the value output and fed back from the minimum SM value accumulator 72. The value output from the minimum SM value accumulator 72 and the pulse generated at the timer 71 are supplied to the register 73.
The operation of the accumulator 61 shown in FIG. 13 will be explained referring to the timing chart in FIGS. 14A to 14D. The pulse generated by the timer 71 (FIG. 14A) is a reset pulse for resetting the cumulative total of the minimum SM values. The minimum SM value accumulator 72 cumulatively adds the minimum SM values input between the pulse generated at a predetermined time t and the pulse generated at the next time t+1 and outputs the value to the register 73.
When the minimum SM value accumulator 72 receives as input a value such as shown in FIG. 14B as the minimum SM value, a cumulative value shown in FIG. 14C is output. That is, when receiving as input a pulse from the timer 71 at the time t, the minimum SM value accumulator 72 resets the cumulative total to 0. It then successively cumulatively adds the minimum SM values input between t and t+1. Further, when a pulse from the timer 71 is input again at the time t+1, the cumulative total is reset to 0.
The register 73 stores the value input from the minimum SM value accumulator 72 at the time when the pulse is input from the timer 71 and outputs the value to the table 62.
FIGS. 15A and 15B are views of an example of a table stored in the table 62. When the transmission system is QPSK and the coding rate R is 1/2, the magnitude of the transmission error rate (C/N) of data on the channel is judged in accordance with the table shown in FIG. 15A. When the transmission system is QPSK and the coding rate R is 3/4, the magnitude of the transmission error rate of the data on the channel is judged in accordance with the table shown in FIG. 15B.
Judging the error rate on the channel as described above required the minimum value processor 52 for calculating the value of the minimum state metric, the minimum SM value accumulator 72 provided at the monitoring circuit 11 and cumulatively adding the output from the minimum value processor 52, and the register 73 for storing the cumulative total. There was the problem that these circuits (apparatuses) 52, 72, and 73 became larger in circuit size along with an increase in the number of transmission signal points (number of states) transmitted from the transmitter 1 (four states in the above example).
Further, there was the problem that the calculation time also increased along with an increase in the number of states. Furthermore, in the BS transmission system, it is being proposed to transmit using different transmission systems for time division. When a plurality of transmission systems are used, there was the problem that, with the monitoring circuit 11 shown in FIG. 12, it became difficult to judge the transmission error rate.